In order to use the IP Integrator and generate a bitstream file, the project will need to be built through Vivado's TCL console. If you only want the source code, the HDL (hardware descriptive language) files can be found under src/hdl. The project is provided, build-able through a TCL script. We will also use a new feature of Vivado 2016.2, Add Module in the IP Integrator, which makes prototyping of complex projects relatively easy, as we will be able to skip the step of writing an HDL wrapper file and easily see how our modules are connected together and interact. This project is intended as a introduction to production of sine waves using an FPGA, a critical step in starting a number of more complex projects, such as driving audio hardware and other analog circuits. We will create a Verilog project for the Digilent Zybo to create a 1 Kilohertz sine wave on the output pins of a Digilent Pmod R2R.
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